The demand for high performance computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. A number of different approaches have been taken to decrease instruction execution time, thereby increasing processor throughput. One way to increase processor throughput is to use a pipeline architecture in which the processor is divided into separate processing stages that form the pipeline. Instructions are broken down into elemental steps that are executed in different stages in an assembly line fashion.
A pipelined processor is capable of executing several different machine instructions concurrently. This is accomplished by breaking down the processing steps for each instruction into several discrete processing phases, each of which is executed by a separate pipeline stage. Hence, each instruction must pass sequentially through each pipeline stage in order to complete its execution. In general, a given instruction is processed by only one pipeline stage at a time, with one clock cycle being required for each stage. Since instructions use the pipeline stages in the same order and typically only stay in each stage for a single clock cycle, an N stage pipeline is capable of simultaneously processing N instructions. When filled with instructions, a processor with N pipeline stages completes one instruction each clock cycle.
The execution rate of an N-stage pipeline processor is theoretically N times faster than an equivalent non-pipelined processor. A non-pipelined processor is a processor that completes execution of one instruction before proceeding to the next instruction. Typically, pipeline overheads and other factors decrease somewhat the execution advantage rate that a pipelined processor has over a non-pipelined processor.
An exemplary seven stage processor pipeline may consist of an address generation stage, an instruction fetch stage, a decode stage, a read stage, a pair of execution (E1 and E2) stages, and a write (or write-back) stage. In addition, the processor may have an instruction cache that stores program instructions for execution, a data cache that temporarily stores data operands that otherwise are stored in processor memory, and a register file that also temporarily stores data operands.
The address generation stage generates the address of the next instruction to be fetched from the instruction cache. The instruction fetch stage fetches an instruction for execution from the instruction cache and stores the fetched instruction in an instruction buffer. The decode stage takes the instruction from the instruction buffer and decodes the instruction into a set of signals that can be directly used for executing subsequent pipeline stages. The read stage fetches required operands from the data cache or registers in the register file. The E1 and E2 stages perform the actual program operation (e.g., add, multiply, divide, and the like) on the operands fetched by the read stage and generates the result. The write stage then writes the result generated by the E1 and E2 stages back into the data cache or the register file.
Assuming that each pipeline stage completes its operation in one clock cycle, the exemplary seven stage processor pipeline takes seven clock cycles to process one instruction. As previously described, once the pipeline is full, an instruction can theoretically be completed every clock cycle.
The throughput of a processor also is affected by the size of the instruction set executed by the processor and the resulting complexity of the instruction decoder. Large instruction sets require large, complex decoders in order to maintain a high processor throughput. However, large complex decoders tend to increase power dissipation, die size and the cost of the processor. The throughput of a processor also may be affected by other factors, such as exception handling, data and instruction cache sizes, multiple parallel instruction pipelines, and the like. All of these factors increase or at least maintain processor throughput by means of complex and/or redundant circuitry that simultaneously increases power dissipation, die size and cost.
In many processor applications, the increased cost, increased power dissipation, and increased die size are tolerable, such as in personal computers and network servers that use x86-based processors. These types of processors include, for example, Intel Pentium™ processors and AMD Athlon™ processors. However, in many applications it is essential to minimize the size, cost, and power requirements of a data processor. This has led to the development of processors that are optimized to meet particular size, cost and/or power limits. For example, the recently developed Transmeta Crusoe™ processor reduces the amount of power consumed by the processor when executing most x86 based programs. This is particularly useful in laptop computer applications. Other types of data processors may be optimized for use in consumer appliances (e.g., televisions, video players, radios, digital music players, and the like) and office equipment (e.g., printers, copiers, fax machines, telephone systems, and other peripheral devices).
In general, an important design objective for data processors used in consumer appliances and office equipment is the minimization of cost and complexity of the data processor. One way to minimize cost and complexity is to exclude from the processor core functions that can be implemented with memory-mapped peripherals external to the core. For example, cache flushing may be performed using a small memory-mapped device controlled by a specialized software function. The cost and complexity of a data processor may also minimized by implementing extremely simple exception behavior in the processor core.
As noted above, a wide-issue processor pipeline executes bundles of operations in multiple stages. In a wide-issue processor, multiple concurrent operations are bundled into a single instruction and are issued and executed as a unit. In a clustered architecture, the machine resources are divided into clusters where each cluster consists of one or more register files each of which is associated with a subset of the execution units of the data processor. Communication between clusters is generally restricted, which presents a significant problem when executing branch instructions—instructions requiring the “jumps” within program execution steps. In such clusters, branch conditions require large amounts of replicated processing resources or an abundance of global communication wires. Once implemented, such processors are commonly rigid, which precludes any reasonable degree of scalability in the branching architecture.
Two architectures that include partitioned register files, address the foregoing problem in different ways. First, there is the Multiflow Trace architecture which allows multiple branches per cycle (or multi-way branches). This implementation requires that each cluster have its own branch unit that uses local conditions and targets, as well as a global controller, to select a final next program counter address. One major disadvantage of the Multiflow Trace architecture is a requirement of large global communication to perform a branch, which detrimentally impacts both speed and solution cost. Another major disadvantage of the Multiflow Trace architecture is that it is not reasonably possible to use data in one cluster to trigger a branch in another cluster.
Second, there is the Texas Instruments TMS3420C6000 architecture, which allows one branch per cluster (with restrictions). However, multiple branches in one bundle cause undefined behavior when more than one branch condition is a “true” condition. In other words, the Texas Instruments TMS3420C6000 architecture only supports single-way branches that can be executed on any cluster. This has disadvantages similar to the Multiflow Trace architecture, namely, long connection paths, need to move branch targets to a “global controller,” etc.
Therefore, there is a need in the art for improved data processors in which the cost and complexity of the processor core is minimized while maintaining the processor throughput. In particular, there is a need for improved systems and methods for executing conditional branch instructions in a data processor. More particularly, there is a need for systems and methods capable of addressing the problem of using remote branch conditions, while maintaining a local branch address computation, avoiding large amounts of global communication, and enabling a relatively good degree of scalability in the branch architecture.
Another way to minimize cost and complexity is to exclude from the processor core functions that can be implemented with memory-mapped peripherals external to the core. For example, cache flushing may be performed using a small memory-mapped device controlled by a specialized software function. The cost and complexity of a data processor may also be minimized by implementing extremely simple exception behavior in the processor core.
A wide-issue processor pipeline, in contrast, executes bundles of operations in multiple stages. In a wide-issue processor, multiple concurrent operations are bundled into a single instruction and are issued and executed as a unit. In a clustered architecture, the machine resources are divided into clusters where each cluster consists of one or more register files each of which is associated with a subset of the execution units of the data processor.
A problem exists in that, to process these bundled instructions, the wide-issue processor pipeline consumes a large amount of power. For instance, a wide-issue processor will commonly execute “bundles” of operations in multiple stages, wherein each stage in the pipeline is as wide as the executed word. Because it is generally not possible to completely populate a wide instruction with useful work (i.e., instructions), it is necessary to insert “dummy” instructions (i.e., non-operations) to fill all available slots. The problem arises in that these inserted “dummy” instructions consume power at each stage. Additionally, in normal operation, wide-issue processors require insertion of explicit non-operations to schedule correctly program execution (i.e., a feature of wide-issue processors over traditional sequential processors), and these non-operations also consume power at each execution stage. As another example, power consumption problems can occur when repeated processor execution of small code sequences occurs as tight loops while unnecessary time is spent and power is expended in the cache.
Many data processors are not designed with a low/no power consumption mode, let alone functional units of the same, and, therefore, power consumption cannot be sufficiently reduced. Excessive power consumption by wide-issue data processors remains a continuing problem.
Therefore, there is also a need in the art for improved data processors in which the cost and complexity of the processor core is minimized while maintaining the processor throughput. In particular, there is a need for improved systems and methods for reducing power consumption in a wide-issue data processor. More particularly, there is a need for systems and methods capable of addressing wasted power and time associated with unnecessary cache accesses.